Mitesh Meswani
Mitesh R. Meswani (AT)
Performance Modeling and Characterization Lab (PMaC)
San Diego Supercomputer Center (SDSC)
University of California, San Deigo
9500 Gilman Drive,
La Jolla, CA 92093-0505
Phone : +1 (858) 534 5072
mitesh AT sdsc DOT edu
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Selected Publications:
(for a full list, please take a look at the CV)
  • Tools for Benchmarking, Tracing, and Simulating SHMEM Applications
    Mitesh R. Meswani Laura Carrington, Allan Snavely, and Stephen Poole
    In The Cray User Group (CUG) Conference,, Germany, April 2012
  • Modeling and Predicting Performance of HPC Applications on Hardware Accelerators
    Mitesh R. Meswani Laura Carrington,Didem Unat, Allan Snavely, Scott Baden, and Stephen Poole
    In proceedings of The Second Workshop on Accelerators and Hybrid Exascale Systems (AsHES) , held in conjunction with IPDPS (AsHES'12), Shanghai, China, May 2012
  • Modeling and Predicting disk I/O on flash systems
    Mitesh R. Meswani J. He, P. Ciocitti, and A. Snavely
    In proceedings of the Workshop on the Appplication of Communication Theory to Emerging Memory Technologies , Miami, Dec 2010.
  • Evaluating the Performance Impact of Hardware Thread Priorities in Simultaneous Multithreaded Processors s using SPEC CPU2000
    Mitesh R. Meswani and Patricia J. Teller
    In proceedings of the 2nd International Workshop on Operating System Interference in High Performance Applications, in conjunctionn with the PACT06 Conference , Seattle, WA, Sept 2006.
  • Profiling Memory Subsystem Performance in an Advanced POWER Virtualization Environment
    Diana Villa, Mitesh R. Meswani Patricia J. Teller, and Bret Olszewski
    In proceedings of the t International Workshop on Operating System Interference in High Performance Applications, in conjunction with the PACT05 Conference, St. Louis, MO, Sept 2005.
Conference Posters:
  • Improved Throughput of Simultaneous Multithreaded (SMT) Processors using SMT Thread Signatures and Hardware Thread Priorities.
    Mitesh R. Meswani Patricia J. Teller, and Sarala Arunagiri
    Poster at the 10th LCI International Conference on High-Performance Clustered Computing (LCI'09), Bolder, CO, March 2009.
  • Measuring and Validating Metrics used to Estimate Microarchitecture Resource Utilization: A Case Study of the IBM POWER5 Processor.
    Mitesh R. Meswani Patricia J. Teller, and Sarala Arunagiri
    Poster at the 2008 ITEA Live-Virtual-Constructive Conference, El Paso, TX, Jan 2009.
Copyright: Mitesh R. Meswani, 2012. Page design adapted from: Grad. Student Template