• High Performance Computing
• Computer Architecture
• Performance Analysis and Modeling
• Hardware Accelerators

Mitesh Meswani received his Ph.D. degree from the University of Texas, El Paso. His dissertation research was in computer systems and implemented a novel modeling approach to improve throughput of Simultaneous Multithreaded (SMT) Processors.

Mitesh Meswani works as a senior computational scientist at the Performance Modeling and Characterization Lab (PMaC). Mitesh Meswani is intersted in modeling and design of emerging technologies for processing, memory, and I/O to improve the execution efficiency on HPC platforms. He is also interested in communication modeling and use of runtime adaptation to improve energy efficiency.

Highlighted Project:
Hardware Accelerator Modeling at San Diego Supercomputer Center
This project evaluates and models the use of hardware accelerators such as GPUs and FPGAs to reduce application runtime. The models are based on identification of compute and memory patterns in code sections that can run faster on accelerators. The project has developed models that can accurately predict speedup for 8 commonly found patterns and is then used to accurately predict overall application speedup.