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00001 
00002 /*********************************************************************
00003 D    2    _    _    60            tdi                    Trap Doubleword Immediate
00004 D    3    _    _    60            twi                    Trap Word Immediate
00005 D    7    _    _    54            mulli                Multiply Low Immediate
00006 D    8    _    SR    51            subfic                Subtract From Immediate Carrying
00007 D    10    _    _    59            cmpli                Compare Logical Immediate
00008 D    11    _    _    58            cmpi                Compare Immediate
00009 D    12    _    SR    50            addic                Add Immediate Carrying
00010 D    13    _    SR    50            addic.                Add Immediate Carrying and Record
00011 D    14    _    _    49            addi                Add Immediate
00012 D    15    _    _    49            addis                Add Immediate Shifted
00013 B    16    _    CT    23            bc[l][a]            Branch Conditional
00014 Sc    17    _    _    25            sc                    System Call
00015 I    18    _    _    23            b[l][a]                Branch
00016 Xl    19    0    _    28            mcrf                Move Condition Register Field
00017 Xl    19    16    CT    24            bclr[l]                Branch Conditional to Link Register
00018 Xl    19    18    _    III            rfid                Return from Interrupt Doubleword
00019 Xl    19    33    _    27            crnor                Condition Register NOR
00020 Xl    19    129    _    27            crandc                Condition Register AND with Complement
00021 Xl    19    150    _    II            isync                Instruction Synchronize
00022 Xl    19    193    _    26            crxor                Condition Register XOR
00023 Xl    19    225    _    26            crnand                Condition Register NAND
00024 Xl    19    257    _    26            crand                Condition Register AND
00025 Xl    19    289    _    27            creqv                Condition Register Equivalent
00026 Xl    19    417    _    27            crorc                Condition Register OR with Complement
00027 Xl    19    449    _    26            cror                Condition Register OR
00028 Xl    19    528    CT    24            bcctr[l]            Branch Conditional to Count Register
00029 M    20    _    SR    73            rlwimi[.]            Rotate Left Word Immediate then Mask Insert
00030 M    21    _    SR    70            rlwinm[.]            Rotate Left Word Immediate then AND with Mask
00031 M    23    _    SR    72            rlwnm[.]            Rotate Left Word then AND with Mask
00032 D    24    _    _    63            ori                    OR Immediate
00033 D    25    _    _    63            oris                OR Immediate Shifted
00034 D    26    _    _    63            xori                XOR Immediate
00035 D    27    _    _    63            xoris                XOR Immediate Shifted
00036 D    28    _    SR    62            andi.                AND Immediate
00037 D    29    _    SR    62            andis.                AND Immediate Shifted
00038 Md    30    0    SR    69            rldicl[.]            Rotate Left Doubleword Immediate then Clear Left
00039 Md    30    1    SR    69            rldicr[.]            Rotate Left Doubleword Immediate then Clear Right
00040 Md    30    2    SR    70            rldic[.]            Rotate Left Doubleword Immediate then Clear
00041 Md    30    3    SR    73            rldimi[.]            Rotate Left Doubleword Immediate then Mask Insert
00042 Mds    30    8    SR    71            rldcl[.]            Rotate Left Doubleword then Clear Left
00043 Mds    30    9    SR    72            rldcr[.]            Rotate Left Doubleword then Clear Right
00044 X    31    0    _    58            cmp                    Compare
00045 X    31    4    _    61            tw                    Trap Word
00046 Xo    31    8    SR    51            subfc[o][.]            Subtract From Carrying
00047 Xo    31    9    SR    55            mulhdu[.]            Multiply High Doubleword Unsigned
00048 Xo    31    10    SR    51            addc[o][.]            Add Carrying
00049 Xo    31    11    SR    55            mulhwu[.]            Multiply High Word Unsigned
00050 Xfx    31    19    _    80            mfcr                Move From Condition Register
00051 Xfx    31    19    _    118            mfocrf                Move From One Condition Register Field
00052 X    31    20    _    II            lwarx                Load Word And Reserve Indexed
00053 X    31    21    _    37            ldx                    Load Doubleword Indexed
00054 X    31    23    _    35            lwzx                Load Word and Zero Indexed
00055 X    31    24    SR    74            slw[.]                Shift Left Word
00056 X    31    26    SR    67            cntlzw[.]            Count Leading Zeros Word
00057 X    31    27    SR    74            sld[.]                Shift Left Doubleword
00058 X    31    28    SR    64            and[.]                AND
00059 X    31    32    _    59            cmpl                Compare Logical
00060 Xo    31    40    SR    50            subf[o][.]            Subtract From
00061 X    31    53    _    37            ldux                Load Doubleword with Update Indexed
00062 X    31    54    _    II            dcbst                Data Cache Block Store
00063 X    31    55    _    35            lwzux                Load Word and Zero with Update Indexed
00064 X    31    58    SR    67            cntlzd[.]            Count Leading Zeros Doubleword
00065 X    31    60    SR    65            andc[.]                AND with Complement
00066 X    31    68    _    61            td                    Trap Doubleword
00067 Xo    31    73    SR    55            mulhd[.]            Multiply High Doubleword
00068 Xo    31    75    SR    55            mulhw[.]            Multiply High Word
00069 X    31    83    _    III            mfmsr                Move From Machine State Register
00070 X    31    84    _    II            ldarx                Load Doubleword And Reserve Indexed
00071 X    31    86    _    II            dcbf                Data Cache Block Flush
00072 X    31    87    _    32            lbzx                Load Byte and Zero Indexed
00073 Xo    31    104    SR    53            neg[o][.]            Negate
00074 X    31    119    _    32            lbzux                Load Byte and Zero with Update Indexed
00075 X    31    124    SR    65            nor[.]                NOR
00076 Xo    31    136    SR    52            subfe[o][.]            Subtract From Extended
00077 Xo    31    138    SR    52            adde[o][.]            Add Extended
00078 Xfx    31    144    _    80            mtcrf                Move To Condition Register Fields
00079 Xfx    31    144    _    118            mtocrf                Move To One Condition Register Field
00080 X    31    146    _    III            mtmsr                Move To Machine State Register
00081 X    31    149    _    41            stdx                Store Doubleword Indexed
00082 X    31    150    _    II            stwcx.                Store Word Conditional Indexed
00083 X    31    151    _    40            stwx                Store Word Indexed
00084 X    31    178    _    III            mtmsrd                Move To Machine State Register Doubleword
00085 X    31    181    _    41            stdux                Store Doubleword with Update Indexed
00086 X    31    183    _    40            stwux                Store Word with Update Indexed
00087 Xo    31    200    SR    53            subfze[o][.]        Subtract From Zero Extended
00088 Xo    31    202    SR    53            addze[o][.]            Add to Zero Extended
00089 X    31    210    32    III            mtsr                Move To Segment Register
00090 X    31    214    _    II            stdcx.                Store Doubleword Conditional Indexed
00091 X    31    215    _    38            stbx                Store Byte Indexed
00092 Xo    31    232    SR    52            subfme[o][.]        Subtract From Minus One Extended
00093 Xo    31    233    SR    54            mulld[o][.]            Multiply Low Doubleword
00094 Xo    31    234    SR    52            addme[o][.]            Add to Minus One Extended
00095 Xo    31    235    SR    54            mullw[o][.]            Multiply Low Word
00096 X    31    242    32    III            mtsrin                Move To Segment Register Indirect
00097 X    31    246    _    II            dcbtst                Data Cache Block Touch for Store
00098 X    31    247    _    38            stbux                Store Byte with Update Indexed
00099 Xo    31    266    SR    50            add[o][.]            Add
00100 X    31    278    _    II            dcbt                Data Cache Block Touch
00101 X    31    279    _    33            lhzx                Load Halfword and Zero Indexed
00102 X    31    284    SR    65            eqv[.]                Equivalent
00103 X    31    306    64    III            tlbie                TLB Invalidate Entry
00104 X    31    310    _    II            eciwx                External Control In Word Indexed
00105 X    31    311    _    33            lhzux                Load Halfword and Zero with Update Indexed
00106 X    31    316    SR    64            xor[.]                XOR
00107 Xfx    31    339    _    79            mfspr                Move From Special Purpose Register
00108 X    31    341    _    36            lwax                Load Word Algebraic Indexed
00109 X    31    343    _    34            lhax                Load Halfword Algebraic Indexed
00110 X    31    370    _    III            tlbia                TLB Invalidate All
00111 Xfx    31    371    _    II            mftb                Move From Time Base
00112 X    31    373    _    36            lwaux                Load Word Algebraic with Update Indexed
00113 X    31    375    _    34            lhaux                Load Halfword Algebraic with Update Indexed
00114 X    31    402    _    III            slbmte                SLB Move To Entry
00115 X    31    407    _    39            sthx                Store Halfword Indexed
00116 X    31    412    SR    65            orc[.]                OR with Complement
00117 Xs    31    413    SR    76            sradi[.]            Shift Right Algebraic Doubleword Immediate
00118 X    31    434    _    III            slbie                SLB Invalidate Entry
00119 X    31    438    _    II            ecowx                External Control Out Word Indexed
00120 X    31    439    _    39            sthux                Store Halfword with Update Indexed
00121 X    31    444    SR    64            or[.]                OR
00122 Xo    31    457    SR    57            divdu[o][.]            Divide Doubleword Unsigned
00123 Xo    31    459    SR    57            divwu[o][.]            Divide Word Unsigned
00124 Xfx    31    467    _    78            mtspr                Move To Special Purpose Register
00125 X    31    476    SR    64            nand[.]                NAND
00126 Xo    31    489    SR    56            divd[o][.]            Divide Doubleword
00127 Xo    31    491    SR    56            divw[o][.]            Divide Word
00128 X    31    498    _    III            slbia                SLB Invalidate All
00129 X    31    512    _    131            mcrxr                Move to Condition Register from XER
00130 X    31    533    _    46            lswx                Load String Word Indexed
00131 X    31    534    _    42            lwbrx                Load Word Byte-Reverse Indexed
00132 X    31    535    _    98            lfsx                Load Floating-Point Single Indexed
00133 X    31    536    SR    75            srw[.]                Shift Right Word
00134 X    31    539    SR    75            srd[.]                Shift Right Doubleword
00135 X    31    566    _    III            tlbsync                TLB Synchronize
00136 X    31    567    _    98            lfsux                Load Floating-Point Single with Update Indexed
00137 X    31    595    32    III            mfsr                 Move From Segment Register
00138 X    31    597    _    46            lswi                Load String Word Immediate
00139 X    31    598    _    II            sync                Synchronize
00140 X    31    599    _    99            lfdx                Load Floating-Point Double Indexed
00141 X    31    631    _    99            lfdux                Load Floating-Point Double with Update Indexed
00142 X    31    659    32    III            mfsrin                Move From Segment Register Indirect
00143 X    31    661    _    47            stswx                Store String Word Indexed
00144 X    31    662    _    43            stwbrx                Store Word Byte-Reverse Indexed
00145 X    31    663    _    101            stfsx                Store Floating-Point Single Indexed
00146 X    31    695    _    101            stfsux                Store Floating-Point Single with Update Indexed
00147 X    31    725    _    47            stswi                Store String Word Immediate
00148 X    31    727    _    102            stfdx                Store Floating-Point Double Indexed
00149 X    31    759    _    102            stfdux                Store Floating-Point Double with Update Indexed
00150 X    31    790    _    42            lhbrx                Load Halfword Byte-Reverse Indexed
00151 X    31    792    SR    77            sraw[.]                Shift Right Algebraic Word
00152 X    31    794    SR    77            srad[.]                Shift Right Algebraic Doubleword
00153 X    31    824    SR    76            srawi[.]            Shift Right Algebraic Word Immediate
00154 X    31    851    _    III            slbmfev                SLB Move From Entry VSID
00155 X    31    854    _    II            eieio                Enforce In-order Execution of I/O
00156 X    31    915    _    III            slbmfee                SLB Move From Entry ESID
00157 X    31    918    _    43            sthbrx                Store Halfword Byte-Reverse Indexed
00158 X    31    922    SR    66            extsh[.]            Extend Sign Halfword
00159 X    31    954    SR    66            extsb[.]            Extend Sign Byte
00160 X    31    982    _    II            icbi                Instruction Cache Block Invalidate
00161 X    31    983    _    103            stfiwx                Store Floating-Point as Integer Word Indexed
00162 X    31    986    SR    66            extsw[.]            Extend Sign Word
00163 X    31    1014    _    II        dcbz                Data Cache Block set to Zero
00164 D    32    _    _    35            lwz                    Load Word and Zero
00165 D    33    _    _    35            lwzu                Load Word and Zero with Update
00166 D    34    _    _    32            lbz                    Load Byte and Zero
00167 D    35    _    _    32            lbzu                Load Byte and Zero with Update
00168 D    36    _    _    40            stw                    Store Word
00169 D    37    _    _    40            stwu                Store Word with Update
00170 D    38    _    _    38            stb                    Store Byte
00171 D    39    _    _    38            stbu                Store Byte with Update
00172 D    40    _    _    33            lhz                    Load Halfword and Zero
00173 D    41    _    _    33            lhzu                Load Halfword and Zero with Update
00174 D    42    _    _    34            lha                    Load Halfword Algebraic
00175 D    43    _    _    34            lhau                Load Halfword Algebraic with Update
00176 D    44    _    _    39            sth                    Store Halfword
00177 D    45    _    _    39            sthu                Store Halfword with Update
00178 D    46    _    _    44            lmw                    Load Multiple Word
00179 D    47    _    _    44            stmw                Store Multiple Word
00180 D    48    _    _    98            lfs                    Load Floating-Point Single
00181 D    49    _    _    98            lfsu                Load Floating-Point Single with Update
00182 D    50    _    _    99            lfd                    Load Floating-Point Double
00183 D    51    _    _    99            lfdu                Load Floating-Point Double with Update
00184 D    52    _    _    101            stfs                Store Floating-Point Single
00185 D    53    _    _    101            stfsu                Store Floating-Point Single with Update
00186 D    54    _    _    102            stfd                Store Floating-Point Double
00187 D    55    _    _    102            stfdu                Store Floating-Point Double with Update
00188 Ds    58    0    _    37            ld                    Load Doubleword
00189 Ds    58    1    _    37            ldu                    Load Doubleword with Update
00190 Ds    58    2    _    36            lwa                    Load Word Algebraic
00191 A    59    18    _    106            fdivs[.]            Floating Divide Single
00192 A    59    20    _    105            fsubs[.]            Floating Subtract Single
00193 A    59    21    _    105            fadds[.]            Floating Add Single
00194 A    59    22    _    120            fsqrts[.]            Floating Square Root Single
00195 A    59    24    _    120            fres[.]                Floating Reciprocal Estimate Single
00196 A    59    25    _    106            fmuls[.]            Floating Multiply Single
00197 A    59    28    _    107            fmsubs[.]            Floating Multiply-Subtract Single
00198 A    59    29    _    107            fmadds[.]            Floating Multiply-Add Single
00199 A    59    30    _    108            fnmsubs[.]            Floating Negative Multiply-Subtract Single
00200 A    59    31    _    108            fnmadds[.]            Floating Negative Multiply-Add Single
00201 Ds    62    0    _    41            std                    Store Doubleword
00202 Ds    62    1    _    41            stdu                Store Doubleword with Update
00203 X    63    0    _    113            fcmpu                Floating Compare Unordered
00204 X    63    12    _    109            frsp[.]                Floating Round to Single-Precision
00205 X    63    14    _    111            fctiw[.]            Floating Convert To Integer Word
00206 X    63    15    _    111            fctiwz[.]            Floating Convert To Integer Word with round toward Zero
00207 A    63    18    _    106            fdiv[.]                Floating Divide
00208 A    63    20    _    105            fsub[.]                Floating Subtract
00209 A    63    21    _    105            fadd[.]                Floating Add
00210 A    63    22    _    120            fsqrt[.]            Floating Square Root
00211 A    63    23    _    121            fsel[.]                Floating Select
00212 A    63    25    _    106            fmul[.]                Floating Multiply
00213 A    63    26    _    121            frsqrte[.]            Floating Reciprocal Square Root Estimate
00214 A    63    28    _    107            fmsub[.]            Floating Multiply-Subtract
00215 A    63    29    _    107            fmadd[.]            Floating Multiply-Add
00216 A    63    30    _    108            fnmsub[.]            Floating Negative Multiply-Subtract
00217 A    63    31    _    108            fnmadd[.]            Floating Negative Multiply-Add
00218 X    63    32    _    113            fcmpo                Floating Compare Ordered
00219 X    63    38    _    116            mtfsb1[.]            Move To FPSCR Bit 1
00220 X    63    40    _    104            fneg[.]                Floating Negate
00221 X    63    64    _    114            mcrfs                Move to Condition Register from FPSCR
00222 X    63    70    _    116            mtfsb0[.]            Move To FPSCR Bit 0
00223 X    63    72    _    104            fmr[.]                Floating Move Register
00224 X    63    134    _    115            mtfsfi[.]            Move To FPSCR Field Immediate
00225 X    63    136    _    104            fnabs[.]            Floating Negative Absolute Value
00226 X    63    264    _    104            fabs[.]                Floating Absolute Value
00227 X    63    583    _    114            mffs[.]                Move From FPSCR
00228 Xfl    63    711    _    115            mtfsf[.]            Move To FPSCR Fields
00229 X    63    814    _    110            fctid[.]            Floating Convert To Integer Doubleword
00230 X    63    815    _    110            fctidz[.]            Floating Convert To Integer Doubleword with round toward
00231 X    63    846    _    112            fcfid[.]            Floating Convert From Integer Doubleword
00232 *********************************************************************/
00233 
00234 
00235 #define    opcode_Tdi       2
00236 #define    opcode_Twi       3
00237 #define    opcode_Mulli     7
00238 #define    opcode_Subfic    8
00239 #define    opcode_Cmpli     10
00240 #define    opcode_Cmpi      11
00241 #define    opcode_Addic     12
00242 #define    opcode_Addicc    13
00243 #define    opcode_Addi      14
00244 #define    opcode_Addis     15
00245 #define    opcode_BcLA      16
00246 #define    opcode_Sc        17
00247 #define    opcode_BLA       18
00248 #define    opcode_Mcrf      19
00249 #define    opcode_BclrL     19
00250 #define    opcode_Rfid      19
00251 #define    opcode_Crnor     19
00252 #define    opcode_Crandc    19
00253 #define    opcode_Isync     19
00254 #define    opcode_Crxor     19
00255 #define    opcode_Crnand    19
00256 #define    opcode_Crand     19
00257 #define    opcode_Creqv     19
00258 #define    opcode_Crorc     19
00259 #define    opcode_Cror      19
00260 #define    opcode_BcctrL    19
00261 #define    opcode_RlwimiC   20
00262 #define    opcode_RlwinmC   21
00263 #define    opcode_RlwnmC    23
00264 #define    opcode_Ori       24
00265 #define    opcode_Oris      25
00266 #define    opcode_Xori      26
00267 #define    opcode_Xoris     27
00268 #define    opcode_Andic     28
00269 #define    opcode_Andisc    29
00270 #define    opcode_RldiclC   30
00271 #define    opcode_RldicrC   30
00272 #define    opcode_RldicC    30
00273 #define    opcode_RldimiC   30
00274 #define    opcode_RldclC    30
00275 #define    opcode_RldcrC    30
00276 #define    opcode_Cmp       31
00277 #define    opcode_Tw        31
00278 #define    opcode_SubfcOC   31
00279 #define    opcode_MulhduC   31
00280 #define    opcode_AddcOC    31
00281 #define    opcode_MulhwuC   31
00282 #define    opcode_Mfcr      31
00283 #define    opcode_Mfocrf    31
00284 #define    opcode_Lwarx     31
00285 #define    opcode_Ldx       31
00286 #define    opcode_Lwzx      31
00287 #define    opcode_SlwC      31
00288 #define    opcode_CntlzwC   31
00289 #define    opcode_SldC      31
00290 #define    opcode_AndC      31
00291 #define    opcode_Cmpl      31
00292 #define    opcode_SubfOC    31
00293 #define    opcode_Ldux      31
00294 #define    opcode_Dcbst     31
00295 #define    opcode_Lwzux     31
00296 #define    opcode_CntlzdC   31
00297 #define    opcode_AndcC     31
00298 #define    opcode_Td        31
00299 #define    opcode_MulhdC    31
00300 #define    opcode_MulhwC    31
00301 #define    opcode_Mfmsr     31
00302 #define    opcode_Ldarx     31
00303 #define    opcode_Dcbf      31
00304 #define    opcode_Lbzx      31
00305 #define    opcode_NegOC     31
00306 #define    opcode_Lbzux     31
00307 #define    opcode_NorC      31
00308 #define    opcode_SubfeOC   31
00309 #define    opcode_AddeOC    31
00310 #define    opcode_Mtcrf     31
00311 #define    opcode_Mtocrf    31
00312 #define    opcode_Mtmsr     31
00313 #define    opcode_Stdx      31
00314 #define    opcode_Stwcxc    31
00315 #define    opcode_Stwx      31
00316 #define    opcode_Mtmsrd    31
00317 #define    opcode_Stdux     31
00318 #define    opcode_Stwux     31
00319 #define    opcode_SubfzeOC  31
00320 #define    opcode_AddzeOC   31
00321 #define    opcode_Mtsr      31
00322 #define    opcode_Stdcxc    31
00323 #define    opcode_Stbx      31
00324 #define    opcode_SubfmeOC  31
00325 #define    opcode_MulldOC   31
00326 #define    opcode_AddmeOC   31
00327 #define    opcode_MullwOC   31
00328 #define    opcode_Mtsrin    31
00329 #define    opcode_Dcbtst    31
00330 #define    opcode_Stbux     31
00331 #define    opcode_AddOC     31
00332 #define    opcode_Dcbt      31
00333 #define    opcode_Lhzx      31
00334 #define    opcode_EqvC      31
00335 #define    opcode_Tlbie     31
00336 #define    opcode_Eciwx     31
00337 #define    opcode_Lhzux     31
00338 #define    opcode_XorC      31
00339 #define    opcode_Mfspr     31
00340 #define    opcode_Lwax      31
00341 #define    opcode_Lhax      31
00342 #define    opcode_Tlbia     31
00343 #define    opcode_Mftb      31
00344 #define    opcode_Lwaux     31
00345 #define    opcode_Lhaux     31
00346 #define    opcode_Slbmte    31
00347 #define    opcode_Sthx      31
00348 #define    opcode_OrcC      31
00349 #define    opcode_SradiC    31
00350 #define    opcode_Slbie     31
00351 #define    opcode_Ecowx     31
00352 #define    opcode_Sthux     31
00353 #define    opcode_OrC       31
00354 #define    opcode_DivduOC   31
00355 #define    opcode_DivwuOC   31
00356 #define    opcode_Mtspr     31
00357 #define    opcode_NandC     31
00358 #define    opcode_DivdOC    31
00359 #define    opcode_DivwOC    31
00360 #define    opcode_Slbia     31
00361 #define    opcode_Mcrxr     31
00362 #define    opcode_Lswx      31
00363 #define    opcode_Lwbrx     31
00364 #define    opcode_Lfsx      31
00365 #define    opcode_SrwC      31
00366 #define    opcode_SrdC      31
00367 #define    opcode_Tlbsync   31
00368 #define    opcode_Lfsux     31
00369 #define    opcode_Mfsr      31
00370 #define    opcode_Lswi      31
00371 #define    opcode_Sync      31
00372 #define    opcode_Lfdx      31
00373 #define    opcode_Lfdux     31
00374 #define    opcode_Mfsrin    31
00375 #define    opcode_Stswx     31
00376 #define    opcode_Stwbrx    31
00377 #define    opcode_Stfsx     31
00378 #define    opcode_Stfsux    31
00379 #define    opcode_Stswi     31
00380 #define    opcode_Stfdx     31
00381 #define    opcode_Stfdux    31
00382 #define    opcode_Lhbrx     31
00383 #define    opcode_SrawC     31
00384 #define    opcode_SradC     31
00385 #define    opcode_SrawiC    31
00386 #define    opcode_Slbmfev   31
00387 #define    opcode_Eieio     31
00388 #define    opcode_Slbmfee   31
00389 #define    opcode_Sthbrx    31
00390 #define    opcode_ExtshC    31
00391 #define    opcode_ExtsbC    31
00392 #define    opcode_Icbi      31
00393 #define    opcode_Stfiwx    31
00394 #define    opcode_ExtswC    31
00395 #define    opcode_Dcbz      31
00396 #define    opcode_Lwz       32
00397 #define    opcode_Lwzu      33
00398 #define    opcode_Lbz       34
00399 #define    opcode_Lbzu      35
00400 #define    opcode_Stw       36
00401 #define    opcode_Stwu      37
00402 #define    opcode_Stb       38
00403 #define    opcode_Stbu      39
00404 #define    opcode_Lhz       40
00405 #define    opcode_Lhzu      41
00406 #define    opcode_Lha       42
00407 #define    opcode_Lhau      43
00408 #define    opcode_Sth       44
00409 #define    opcode_Sthu      45
00410 #define    opcode_Lmw       46
00411 #define    opcode_Stmw      47
00412 #define    opcode_Lfs       48
00413 #define    opcode_Lfsu      49
00414 #define    opcode_Lfd       50
00415 #define    opcode_Lfdu      51
00416 #define    opcode_Stfs      52
00417 #define    opcode_Stfsu     53
00418 #define    opcode_Stfd      54
00419 #define    opcode_Stfdu     55
00420 #define    opcode_Ld        58
00421 #define    opcode_Ldu       58
00422 #define    opcode_Lwa       58
00423 #define    opcode_FdivsC    59
00424 #define    opcode_FsubsC    59
00425 #define    opcode_FaddsC    59
00426 #define    opcode_FsqrtsC   59
00427 #define    opcode_FresC     59
00428 #define    opcode_FmulsC    59
00429 #define    opcode_FmsubsC   59
00430 #define    opcode_FmaddsC   59
00431 #define    opcode_FnmsubsC  59
00432 #define    opcode_FnmaddsC  59
00433 #define    opcode_Std       62
00434 #define    opcode_Stdu      62
00435 #define    opcode_Fcmpu     63
00436 #define    opcode_FrspC     63
00437 #define    opcode_FctiwC    63
00438 #define    opcode_FctiwzC   63
00439 #define    opcode_FdivC     63
00440 #define    opcode_FsubC     63
00441 #define    opcode_FaddC     63
00442 #define    opcode_FsqrtC    63
00443 #define    opcode_FselC     63
00444 #define    opcode_FmulC     63
00445 #define    opcode_FrsqrteC  63
00446 #define    opcode_FmsubC    63
00447 #define    opcode_FmaddC    63
00448 #define    opcode_FnmsubC   63
00449 #define    opcode_FnmaddC   63
00450 #define    opcode_Fcmpo     63
00451 #define    opcode_Mtfsb1    63
00452 #define    opcode_FnegC     63
00453 #define    opcode_Mcrfs     63
00454 #define    opcode_Mtfsb0    63
00455 #define    opcode_FmrC      63
00456 #define    opcode_MtfsfiC   63
00457 #define    opcode_FnabsC    63
00458 #define    opcode_FabsC     63
00459 #define    opcode_MffsC     63
00460 #define    opcode_MtfsfC    63
00461 #define    opcode_FctidC    63
00462 #define    opcode_FctidzC   63
00463 #define    opcode_FcfidC    63
00464 
00465 
00466 #define    xcode_Mcrf      0
00467 #define    xcode_BclrL     16
00468 #define    xcode_Rfid      18
00469 #define    xcode_Crnor     33
00470 #define    xcode_Crandc    129
00471 #define    xcode_Isync     150
00472 #define    xcode_Crxor     193
00473 #define    xcode_Crnand    225
00474 #define    xcode_Crand     257
00475 #define    xcode_Creqv     289
00476 #define    xcode_Crorc     417
00477 #define    xcode_Cror      449
00478 #define    xcode_BcctrL    528
00479 #define    xcode_Ld        0
00480 #define    xcode_Ldu       1
00481 #define    xcode_Lwa       2
00482 #define    xcode_FdivsC    18
00483 #define    xcode_FsubsC    20
00484 #define    xcode_FaddsC    21
00485 #define    xcode_FsqrtsC   22
00486 #define    xcode_FresC     24
00487 #define    xcode_FmulsC    25
00488 #define    xcode_FmsubsC   28
00489 #define    xcode_FmaddsC   29
00490 #define    xcode_FnmsubsC  30
00491 #define    xcode_FnmaddsC  31
00492 #define    xcode_Std       0
00493 #define    xcode_Stdu      1
00494 #define    xcode_Fcmpu     0
00495 #define    xcode_FrspC     12
00496 #define    xcode_FctiwC    14
00497 #define    xcode_FctiwzC   15
00498 #define    xcode_FdivC     18
00499 #define    xcode_FsubC     20
00500 #define    xcode_FaddC     21
00501 #define    xcode_FsqrtC    22
00502 #define    xcode_FselC     23
00503 #define    xcode_FmulC     25
00504 #define    xcode_FrsqrteC  26
00505 #define    xcode_FmsubC    28
00506 #define    xcode_FmaddC    29
00507 #define    xcode_FnmsubC   30
00508 #define    xcode_FnmaddC   31
00509 #define    xcode_Fcmpo     32
00510 #define    xcode_Mtfsb1    38
00511 #define    xcode_FnegC     40
00512 #define    xcode_Mcrfs     64
00513 #define    xcode_Mtfsb0    70
00514 #define    xcode_FmrC      72
00515 #define    xcode_MtfsfiC   134
00516 #define    xcode_FnabsC    136
00517 #define    xcode_FabsC     264
00518 #define    xcode_MffsC     583
00519 #define    xcode_MtfsfC    711
00520 #define    xcode_FctidC    814
00521 #define    xcode_FctidzC   815
00522 #define    xcode_FcfidC    846
00523 #define    xcode_RldiclC   0
00524 #define    xcode_RldicrC   1
00525 #define    xcode_RldicC    2
00526 #define    xcode_RldimiC   3
00527 #define    xcode_RldclC    8
00528 #define    xcode_RldcrC    9
00529 #define    xcode_Cmp       0
00530 #define    xcode_Tw        4
00531 #define    xcode_SubfcOC   8
00532 #define    xcode_MulhduC   9
00533 #define    xcode_AddcOC    10
00534 #define    xcode_MulhwuC   11
00535 #define    xcode_Mfcr      19
00536 #define    xcode_Mfocrf    19
00537 #define    xcode_Lwarx     20
00538 #define    xcode_Ldx       21
00539 #define    xcode_Lwzx      23
00540 #define    xcode_SlwC      24
00541 #define    xcode_CntlzwC   26
00542 #define    xcode_SldC      27
00543 #define    xcode_AndC      28
00544 #define    xcode_Cmpl      32
00545 #define    xcode_SubfOC    40
00546 #define    xcode_Ldux      53
00547 #define    xcode_Dcbst     54
00548 #define    xcode_Lwzux     55
00549 #define    xcode_CntlzdC   58
00550 #define    xcode_AndcC     60
00551 #define    xcode_Td        68
00552 #define    xcode_MulhdC    73
00553 #define    xcode_MulhwC    75
00554 #define    xcode_Mfmsr     83
00555 #define    xcode_Ldarx     84
00556 #define    xcode_Dcbf      86
00557 #define    xcode_Lbzx      87
00558 #define    xcode_NegOC     104
00559 #define    xcode_Lbzux     119
00560 #define    xcode_NorC      124
00561 #define    xcode_SubfeOC   136
00562 #define    xcode_AddeOC    138
00563 #define    xcode_Mtcrf     144
00564 #define    xcode_Mtocrf    144
00565 #define    xcode_Mtmsr     146
00566 #define    xcode_Stdx      149
00567 #define    xcode_Stwcxc    150
00568 #define    xcode_Stwx      151
00569 #define    xcode_Mtmsrd    178
00570 #define    xcode_Stdux     181
00571 #define    xcode_Stwux     183
00572 #define    xcode_SubfzeOC  200
00573 #define    xcode_AddzeOC   202
00574 #define    xcode_Mtsr      210
00575 #define    xcode_Stdcxc    214
00576 #define    xcode_Stbx      215
00577 #define    xcode_SubfmeOC  232
00578 #define    xcode_MulldOC   233
00579 #define    xcode_AddmeOC   234
00580 #define    xcode_MullwOC   235
00581 #define    xcode_Mtsrin    242
00582 #define    xcode_Dcbtst    246
00583 #define    xcode_Stbux     247
00584 #define    xcode_AddOC     266
00585 #define    xcode_LscbxC    277
00586 #define    xcode_Dcbt      278
00587 #define    xcode_Lhzx      279
00588 #define    xcode_EqvC      284
00589 #define    xcode_Tlbie     306
00590 #define    xcode_Eciwx     310
00591 #define    xcode_Lhzux     311
00592 #define    xcode_XorC      316
00593 #define    xcode_Mfspr     339
00594 #define    xcode_Lwax      341
00595 #define    xcode_Lhax      343
00596 #define    xcode_Tlbia     370
00597 #define    xcode_Mftb      371
00598 #define    xcode_Lwaux     373
00599 #define    xcode_Lhaux     375
00600 #define    xcode_Slbmte    402
00601 #define    xcode_Sthx      407
00602 #define    xcode_OrcC      412
00603 #define    xcode_SradiC    413
00604 #define    xcode_Slbie     434
00605 #define    xcode_Ecowx     438
00606 #define    xcode_Sthux     439
00607 #define    xcode_OrC       444
00608 #define    xcode_DivduOC   457
00609 #define    xcode_DivwuOC   459
00610 #define    xcode_Mtspr     467
00611 #define    xcode_NandC     476
00612 #define    xcode_DivdOC    489
00613 #define    xcode_DivwOC    491
00614 #define    xcode_Slbia     498
00615 #define    xcode_Mcrxr     512
00616 #define    xcode_Lswx      533
00617 #define    xcode_Lwbrx     534
00618 #define    xcode_Lfsx      535
00619 #define    xcode_SrwC      536
00620 #define    xcode_SrdC      539
00621 #define    xcode_Tlbsync   566
00622 #define    xcode_Lfsux     567
00623 #define    xcode_Mfsr      595
00624 #define    xcode_Lswi      597
00625 #define    xcode_Sync      598
00626 #define    xcode_Lfdx      599
00627 #define    xcode_Lfdux     631
00628 #define    xcode_Mfsrin    659
00629 #define    xcode_Stswx     661
00630 #define    xcode_Stwbrx    662
00631 #define    xcode_Stfsx     663
00632 #define    xcode_Stfsux    695
00633 #define    xcode_Stswi     725
00634 #define    xcode_Stfdx     727
00635 #define    xcode_Stfdux    759
00636 #define    xcode_Lhbrx     790
00637 #define    xcode_SrawC     792
00638 #define    xcode_SradC     794
00639 #define    xcode_SrawiC    824
00640 #define    xcode_Slbmfev   851
00641 #define    xcode_Eieio     854
00642 #define    xcode_Slbmfee   915
00643 #define    xcode_Sthbrx    918
00644 #define    xcode_ExtshC    922
00645 #define    xcode_ExtsbC    954
00646 #define    xcode_Icbi      982
00647 #define    xcode_Stfiwx    983
00648 #define    xcode_ExtswC    986
00649 #define    xcode_Dcbz      1014
00650 
00651 
00652 #define BRANCH_ALWAYS(__ho)  (((__ho) & 0x14) == 0x14)
00653 #define IS_B(__i)            ((__i).opc.opc == opcode_BLA)
00654 #define IS_BC(__i)           ((__i).opc.opc == opcode_BcLA)
00655 #define IS_BCLR(__i)         (((__i).opc.opc == opcode_BclrL) && ((__i).xl.xo == xcode_BclrL))
00656 #define IS_BCCTR(__i)        (((__i).opc.opc == opcode_BcctrL) && ((__i).xl.xo == xcode_BcctrL))
00657 #define IS_CMPLI(__i)        ((__i).opc.opc == opcode_Cmpli)
00658 #define IS_LWZ(__i)          ((__i).opc.opc == opcode_Lwz)
00659 #define IS_LD(__i)           (((__i).opc.opc == opcode_Ld) && ((__i).ds.xo == xcode_Ld))
00660 #define IS_ADD(__i)          (((__i).opc.opc == opcode_AddOC) && ((__i).xo.xo == xcode_AddOC))
00661 #define IS_LDX(__i)          (((__i).opc.opc == opcode_Ldx) && ((__i).x.xo == xcode_Ldx))
00662 #define IS_LWZX(__i)         (((__i).opc.opc == opcode_Lwzx) && ((__i).x.xo == xcode_Lwzx))
00663 #define IS_ADDI(__i)         ((__i).opc.opc == opcode_Addi)
00664 #define IS_LSWI(__i)         (((__i).opc.opc == opcode_Lswi) && ((__i).x.xo == xcode_Lswi))
00665 #define IS_STSWI(__i)        (((__i).opc.opc == opcode_Stswi) && ((__i).x.xo == xcode_Stswi))
00666 
00667 #define GET_BH(__i)          (((__i).xl.bb) & 0x3)
00668 #define REG_TOC              2
00669 #define REG_SP               1
00670 #define INVALID_REGISTER     0xffffffff
00671 #define INVALID_XOP          0x400
00672 
00673 #define MEMORY_MASK          0x1c
00674 #define MEMORY_MATCH         0x14
00675 #define FOP_AFORM_MASK       0x10
00676 #define FOP_AFORM_MATCH      0x10
00677 #define FOP_CONDREG_MASK     0x1e
00678 #define FOP_CONDREG_MATCH    0x06
00679 
00680 #define NUM_OF_GPR_REGS      0x20
00681 #define NUM_OF_FPR_REGS      0x20
00682 #define LAST_VOLATILE_REG    0xd
00683 
00684 #define REG_XER              0x020
00685 #define REG_LNK              0x100
00686 #define REG_CTR              0x120
00687 
00688 #define SAFE_FRAME_LOC       64
00689 
00690 #define COMPARE_LT           0
00691 #define COMPARE_GT           1
00692 #define COMPARE_EQ           2
00693 #define COMPARE_TRUE         1
00694 #define COMPARE_FALSE        0

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